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| a preliminary technical data dsp microcomputer this information applies to a product under development. its characteristics and specifications are subject to change without notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. one technology way, p .o.box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 world wide web site: http://www.analog.com fax:781/326-8703 ?analog devices,inc., 2001 rev. pra adsp-2195 adsp-219x dsp core features 6.25 ns instruction cycle time (internal), for up to 160 mips sustained performance adsp-218x family code compatible with the same easy -to-use algebraic syntax single-cycle instruction execution up to 16m words of addressable memory space with 24 bits of addressing width dual purpose program memory for both instruction and data storage fully transparent instruction cache allows dual operand fetches in every instruction cycle unified memory space permits flexible address generation, using two independent dag units independent alu, multiplier/accumulator, and barrel shifter computational units with dual 40-bit accumulators single-cycle context switch between two sets of computational and dag registers parallel execution of computation and memory instructions pipelined architecture supports efficient code execution at speeds up to 160 mips register file computations with all nonconditional, nonparallel computational instructions powerful program sequencer provides zero-overhead looping and conditional instruction execution architectural enhancements for compiled c code efficiency functional block diagram ! ! ! ! ! "# $ % & & ' & for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 2 rev. pra adsp-2195 dsp features 32k words of on-chip ram, configured as 16k words on-chip 24-bit ram and 16k words on-chip 16-bit ram 16k words of on-chip 24-bit rom architecture enhancements beyond adsp-218x family are supported with instruction set extensions for added registers, ports, and peripherals flexible power management with selectable power-down and idle modes programmable pll supports 1 to 32 frequency multiplication, enabling full-speed operation from low-speed input clocks 2.5 v internal operation supports 3.3 v compliant i/o three full-duplex multichannel serial ports, each supporting h.100 standard with a-law and -law companding in hardware two spi-compatible ports with dma capability one uart port with dma capability 16 general-purpose i/o pins (eight dedicated/eight programmable from the external memory interface) with integrated interrupt support three programmable 32-bit interval timers with pulsewidth counter, pwm generation, and externally clocked timer capabilities up to 11 dma channels can be active at any given time host port with dma capability for efficient, glueless host interface (16-bit transfers) external memory interface features include: direct access from the dsp to external memory for data and instructions. support for dma block transfers to/from external memory. separate peripheral memory space with parallel support for 224k external 16-bit registers. four general-purpose memory select signals that provide access to separate banks of external memory. bank boundaries and size are user- programmable. programmable waitstate logic with ack signal and separate read and write wait counts. wait mode completion supports all combinations of ack and/or wait count. i/o clock rate can be set to the peripheral clock rate divided by 1, 2, 4, 16, or 32 to allow interface to slow memory devices. address translation and data word packing is provided to support an 8- or 16-bit external data bus. programmable read and write strobe polarity. separate configuration registers for the four general-purpose, peripheral, and boot memory spaces. bus request and grant signals support the use of the external bus by an external device. boot methods include booting through external memory interface, spi ports, uart port, or host interface ieee jtag standard 1149.1 test access port supports on-chip emulation and system debugging 144-lead lqfp package (20 20 1.4 mm) and 144-lead mini-bga package (10 10 1.25 mm) this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 3 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 table of contents adsp-219x dsp core features . . . . . . . . . . . . . . . . . 1 functional block diagram. . . . . . . . . . . . . . . . . . . . . . 2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . 4 dsp core architecture . . . . . . . . . . . . . . . . . . . . . . . 4 dsp peripherals architecture . . . . . . . . . . . . . . . . . . . 5 memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . 6 internal (on-chip) memory . . . . . . . . . . . . . . . . 6 internal on-chip rom . . . . . . . . . . . . . . . . . . . . 6 on-chip memory security . . . . . . . . . . . . . . . . . 7 external (off-chip) memory . . . . . . . . . . . . . . . . 8 external memory space . . . . . . . . . . . . . . . . . . . . 8 i/o memory space . . . . . . . . . . . . . . . . . . . . . . . 8 boot memory space . . . . . . . . . . . . . . . . . . . . . . 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 host port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 host port acknowledge (hack) modes . . . . . . 10 host port chip selects . . . . . . . . . . . . . . . . . . . 11 dsp serial ports (sports) . . . . . . . . . . . . . . . . . . . 11 serial peripheral interface (spi) ports . . . . . . . . . . . 11 uart port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 programmable flag (pfx) pins . . . . . . . . . . . . . . . . . 12 low power operation . . . . . . . . . . . . . . . . . . . . . . . 13 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power-down core mode . . . . . . . . . . . . . . . . . . 13 power-down core/peripherals mode . . . . . . . . . 13 power-down all mode . . . . . . . . . . . . . . . . . . . 13 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 booting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bus request and bus grant . . . . . . . . . . . . . . . . . . . 16 instruction set description . . . . . . . . . . . . . . . . . . . . 16 development tools . . . . . . . . . . . . . . . . . . . . . . . . . 16 designing an emulator-compatible dsp board (target) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 target board header . . . . . . . . . . . . . . . . . . . . . 17 jtag emulator pod connector . . . . . . . . . . . . 18 design-for-emulation circuit information . . . . . 18 additional information . . . . . . . . . . . . . . . . . . . . . . . 18 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 recommended operating conditions . . . . . . . . . . 22 electrical characteristics . . . . . . . . . . . . . . . . . . . . 22 absolute maximum ratings . . . . . . . . . . 24 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 24 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 24 clock in and clock out cycle timing . . . . . . . 25 programmable flags cycle timing . . . . . . . . . . 26 timer pwm_out cycle timing . . . . . . . . . . . 27 external port write cycle timing . . . . . . . . . . . 28 external port read cycle timing . . . . . . . . . . . 30 external port bus request and grant cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 host port ale mode write cycle timing . . . . 34 host port acc mode write cycle timing . . . . 36 host port ale mode read cycle timing . . . . . 38 host port acc mode read cycle timing . . . . 40 serial port (sport) clocks and data timing . 42 serial port (sport) frame synch timing . . . . 44 serial peripheral interface (spi) port?master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 serial peripheral interface (spi) port?slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 universal asynchronous receiver-transmitter (uart) port?receive and transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 jtag test and emulation port timing . . . . . . 51 output drive currents . . . . . . . . . . . . . . . . . . . . . . 52 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 52 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 output disable time . . . . . . . . . . . . . . . . . . . . 54 output enable time . . . . . . . . . . . . . . . . . . . . . 54 example system hold time calculation . . . . . . 55 capacitive loading . . . . . . . . . . . . . . . . . . . . . . 55 environmental conditions . . . . . . . . . . . . . . . . . . . . 55 thermal characteristics . . . . . . . . . . . . . . . . . . 55 adsp-2195 144-lead lqfp pinout . . . . . . . . . . . . 58 adsp-2195 144-lead mini-bga pinout . . . . . . . . 67 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 4 rev. pra general note this data sheet provides preliminary information for the adsp-2195 digital signal processor. general description the adsp-2195 dsp is a single-chip microcomputer optimized for digital signal processing (dsp) and other high speed numeric processing applications. the adsp-2195 combines the adsp-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two spi-compatible ports, one uart port, a dma controller, three programmable timers, general-purpose programmable flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces. the adsp-2195 architecture is code-compatible with adsp-218x family dsps. although the architectures are compatible, the adsp-2195 architecture has a number of enhancements over the adsp-218x architecture. the enhancements to computational units, data address gener- ators, and program sequencer make the adsp-2195 more flexible and even easier to program than the adsp-218x dsps. indirect addressing options provide addressing flexibility? premodify with no update, pre- and post-modify by an immediate 8-bit, two?s-complement value and base address registers for easier implementation of circular buffering. the adsp-2195 integrates 48k words of on-chip memory configured as 16k words (24-bit) of program ram, 16k words (16-bit) of data ram, and 16k words (24-bit) of program rom. power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. the adsp-2195 is available in 144-lead lqfp and mini-bga packages. fabricated in a high-speed, low-power, cmos process, the adsp-2195 operates with a 6.25 ns instruction cycle time (160 mips). all instructions, except two multiword instructions, can execute in a single dsp cycle. the adsp-2195?s flexible architecture and comprehensive instruction set support multiple operations in parallel. for example, in one processor cycle, the adsp-2195 can: generate an address for the next instruction fetch fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation these operations take place while the processor continues to: receive and transmit data through two serial ports receive and/or transmit data from a host receive or transmit data through the uart receive or transmit data over two spi ports access external memory through the external memory interface decrement the timers dsp core architecture the adsp-2195 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every single-word instruction can be executed in a single processor cycle. the adsp-2195 assembly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. the functional block diagram on page 1 shows the architec- ture of the adsp-219x core. it contains three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data from the register file and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs sin- gle-cycle multiply, multiply/add, and multiply/subtract operations. the mac has two 40-bit accumulators, which help with overflow. the shifter performs logical and arith- metic shifts, normalization, denormalization, and derive exponent operations. the shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. register-usage rules influence placement of input and results within the computational units. for most operations, the computational units? data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. for feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. for conditional or mul- tifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. for more information, see the adsp-219x dsp instruction set reference . a powerful program sequencer controls the flow of instruc- tion execution. the sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. with internal loop counters and loop stacks, the adsp-2195 executes looped code with zero overhead; no explicit jump instruc- tions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four 16-bit address pointers. whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. a length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. page registers in the dags allow circular addressing this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 5 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 within 64k word boundaries of each of the 256 memory pages, but these buffers may not cross page boundaries. secondary registers duplicate all the primary registers in the dags; switching between primary and secondary registers provides a fast context switch. efficient data transfer in the core is achieved with the use of internal buses: program memory address (pma) bus program memory data (pmd) bus data memory address (dma) bus data memory data (dmd) bus dma address bus dma data bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. boot memory space and i/o memory space also share the external buses. program memory can store both instructions and data, per- mitting the adsp-2195 to fetch two operands in a single cycle, one from program memory and one from data memory. the dsp?s dual memory buses also let the adsp-219x core fetch an operand from data memory and the next instruction from program memory in a single cycle. dsp peripherals architecture the functional block diagram on page 1 shows the dsp?s on-chip peripherals, which include the external memory interface, host port, serial ports, spi-compatible ports, uart port, jtag test and emulation port, timers, flags, and interrupt controller. these on-chip peripherals can connect to off-chip devices as shown in figure 1 . the adsp-2195 has a 16-bit host port with dma capa- bility that lets external hosts access on-chip memory. this 24-pin parallel port consists of a 16-pin multiplexed data/address bus and provides a low-service overhead data move capability. configurable for 8- or 16-bits, this port provides a glueless interface to a wide variety of 8- and 16-bit microcontrollers. two chip-selects provide hosts access to the dsp?s entire memory map. the dsp is bootable through this port. the adsp-2195 also has an external memory interface that is shared by the dsp?s core, the dma controller, and dma capable peripherals, which include the uart, sport0, sport1, sport2, spi0, spi1, and the host port. the external port consists of a 16-bit data bus, a 22-bit address bus, and control signals. the data bus is configurable to provide an 8 or 16 bit interface to external memory. support for word packing lets the dsp access 16- or 24-bit words from external memory regardless of the external data bus width. when configured for an 8-bit interface, the unused eight lines provide eight programmable, bidirectional gen- eral-purpose programmable flag lines, six of which can be mapped to software condition signals. the memory dma controller lets the adsp-2195 move data and instructions from between memory spaces: inter- nal-to-external, internal-to-internal, and external-to- external. on-chip peripherals can also use this controller for dma transfers. the adsp-2195 can respond to up to seventeen interrupts at any given time: three internal (stack, emulator kernel, and power-down), two external (emulator and reset), and twelve user-defined (peripherals) interrupts. programmers assign figure 1. adsp-2195 system diagram ( )* ") *' & % *' +*' )* *' +*' & % ! )* *' +*' & % )* +*' +*' & % ! )*' )*' & % ' )*' % & &, &' ' ' &' ' ' & & & &' ' ' & & ! ! ' & ! *' *' + *' & *' ' ( ( ( & & for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 6 rev. pra a peripheral to one of the 12 user-defined interrupts. these assignments determine the priority of each peripheral for interrupt service. there are three serial ports on the adsp-2195 that provide a complete synchronous, full-duplex serial interface. this interface includes optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each serial port can transmit or receive an internal or external, programmable serial clock and frame syncs. each serial port supports 128-channel time division multiplexing. the adsp-2195 provides up to sixteen general-purpose i/o pins, which are programmable as either inputs or outputs. eight of these pins are dedicated general purpose programmable flag pins. the other eight of them are mul- tifunctional pins, acting as general purpose i/o pins when the dsp connects to an 8-bit external data bus and acting as the upper eight data pins when the dsp connects to a 16-bit external data bus. these programmable flag pins can implement edge- or level-sensitive interrupts, some of which can be used to base the execution of conditional instructions. three programmable interval timers generate periodic interrupts. each timer can be independently set to operate in one of three modes: pulse waveform generation mode pulsewidth count/capture mode external event watchdog mode each timer has one bi-directional pin and four registers that implement its mode of operation: a 7-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulsewidth register. a single status register supports all three timers. a bit in the mode status register globally enables or disables all three timers, and a bit in each timer?s configuration register enables or disables the corresponding timer independently of the others. memory architecture the adsp-2195 dsp provides 32k words of on-chip sram memory. this memory is divided into two 16k blocks located on memory page 0 in the dsp?s memory map. the dsp also provides 16k words of on-chip rom. in addition to the internal and external memory space, the adsp-2195 can address two additional and separate off-chip memory spaces: i/o space and boot space. as shown in figure 2 , the dsp?s two internal memory blocks populate all of page 0. the entire dsp memor y map consists of 256 pages (pages 0 ? 255), and each page is 64k words long. external memory space consists of four memory banks (banks 0?3) and supports a wide variety of sram memory devices. each bank is selectable using the memory select pins (ms3?0 ) and has configurable page boundaries, waitstates, and waitstate modes. the 1k word of on-chip boot-rom populates the top of page 255 while the remaining 254 pages are addressable off-chip. i/o memory pages differ from external memory pages in that i/o pages are 1k word long, and the external i/o pages have their own select pin (ioms ). pages 0?31 of i/o memory space reside on-chip and contain the configuration registers for the peripherals. both the adsp-2195 and dma-capa- ble peripherals can access the dsp?s entire memory map. internal (on-chip) memory the adsp-2195?s unified program and data memory space consists of 16m locations that are accessible through two 24-bit address buses, the pma and dma buses. the dsp uses slightly different mechanisms to generate a 24-bit address for each bus. the dsp has three functions that support access to the full memory map. the dags generate 24-bit addresses for data fetches from the entire dsp memory address range. because dag index (address) registers are 16 bits wide and hold the lower 16 bits of the address, each of the dags has its own 8-bit page register (dmpgx) to hold the most significant eight address bits. before a dag generates an address, the program must set the dag?s dmpgx register to the appropriate memory page. the program sequencer generates the addresses for instruction fetches. for relative addressing instructions, the program sequencer bases addresses for relative jumps, calls, and loops on the 24-bit program counter (pc). in direct addressing instructions (two-word instructions), the instruction provides an immediate 24-bit address value. the pc allows linear addressing of the full 24-bit address range. for indirect jumps and calls that use a 16-bit dag address register for part of the branch address, the program sequencer relies on an 8-bit indirect jump page (ijpg) register to supply the most significant eight address bits. before a cross page jump or call, the program must set the program sequencer?s ijpg register to the appropriate memory page. the adsp-2195 has 1k word of on-chip rom that holds boot routines. if peripheral booting is selected, the dsp starts executing instructions from the on-chip boot rom, which starts the boot process from the selected peripheral. for more information, see booting modes on page 15. the on-chip boot rom is located on page 255 in the dsp?s memory space map. internal on-chip rom the adsp-2195 dsp features a 16k-word 24-bit on-chip maskable rom mapped into program memory space ( figure 3 ). customers can arrange to have the rom programmed with application-specific code. this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 7 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 on-chip memory security the adsp-2195 has a maskable option to protect the contents of on-chip memories from being accessed. when the rom protection is set, the on-chip rom space cannot be accessed by a hardware emulator. figure 2. adsp-2195 memory map figure 3. adsp-2195 memory map, with on-chip rom & & & &' ' ( ( - '#'' '''' '#'' ''' '#' '''' '# ' '''' '#' '''' '# ' '''' '# '''' '# '' '# '#'' ''' '#'' ''' & % ' * *+ *" "*) )) ! ( & & ' & & % . & % *) '#' '''' '# & % *)) & % '*+ % & ! . % & / . '#'' '''' '#'' ''' '#' ! & & & &' ' ( - '#'' '''' '#'' ''' '#' '''' '# ' '''' '#' '''' '# ' '''' '# '''' '# '' '# '#'' ''' '#'' ''' & % ' * *+ *" "*) )) ! ( & & ' & & & % . & % *) '#' '''' '# & % *)) & % '*+ % & ! . % & / . '#'' '''' '#'' ''' '#' ! for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 8 rev. pra external (off-chip) memory each of the adsp-2195?s off-chip memory spaces has a separate control register, so applications can configure unique access parameters for each space. the access param- eters include read and write wait counts, waitstate completion mode, i/o clock divide ratio, write hold time extension, strobe polarity, and data bus width. the core clock and peripheral clock ratios influence the external memory access strobe widths. for more information, see clock signals on page 14. the off-chip memory spaces are: external memory space (ms3?0 pins) i/o memory space (ioms pin) boot memory space (bms pin) all of these off-chip memory spaces are accessible through the external port, which can be configured for 8-bit or 16-bit data widths. external memory space external memory space consists of four memory banks. these banks can contain a configurable number of 64k word pages. at reset, the page boundaries for external memory have bank0 containing pages 1 ? 63, bank1 con- taining pages 64 ? 127, bank2 containing pages 128 ? 191, and bank3 containing pages 192 ? 254. the ms3?0 memory bank pins select banks 3?0, respectively. the external memory interface decodes the 8 msbs of the dsp program address to select one of the four banks. both the adsp-219x core and dma-capable peripherals can access the dsp?s external memory space. i/o memory space the adsp-2195 supports an additional external memory called i/o memory space. this space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface asic data regis- ters. i/o space supports a total of 256k locations. the first 8k addresses are reserved for on-chip peripherals. the upper 248k addresses are available for external peripheral devices. the dsp?s instruction set provides instructions for accessing i/o space. these instructions use an 18-bit address that is assembled from an 8-bit i/o page (iopg) register and a 10-bit immediate value supplied in the instruction. both the adsp-219x core and a host (through the host port interface) can access i/o memory space. boot memory space boot memory space consists of one off-chip bank with 254 pages. the bms memory bank pin selects boot memory space. both the adsp-219x core and dma-capable peripherals can access the dsp?s off-chip boot memory space. after reset, the dsp always starts executing instruc- tions from the on-chip boot rom. depending on the boot configuration, the boot rom code can start booting the dsp from boot memory. for more information, see booting modes on page 15. interrupts the interrupt controller lets the dsp respond to 17 inter- rupts with minimum overhead. the controller implements an interrupt priority scheme as shown in table 1 . applica- tions can use the unassigned slots for software and peripheral interrupts. table 2 shows the id and priority at reset of each of the peripheral interrupts. to assign the peripheral interrupts a different priority, applications write the new priority to their corresponding control bits (determined by their id) in the interrupt priority control register. the peripheral inter- rupt?s position in the imask and irptl register and its vector address depend on its priority level, as shown in table 1 . because the imask and irptl registers are limited to 16 bits, any peripheral interrupts assigned a table 1. interrupt priorities/addresses interrupt imask/ irptl vector address 1 1 these interrupt vectors start at address 0x10000 when the dsp is in ?no-boot?, run-form-external memory mode. emulator (nmi)? highest priority na na reset (nmi) 0 0x00 0000 power-down (nmi) 1 0x00 0020 loop and pc stack 2 0x00 0040 emulation kernel 3 0x00 0060 user assigned interrupt 4 0x00 0080 user assigned interrupt 5 0x00 00a0 user assigned interrupt 6 0x00 00c0 user assigned interrupt 7 0x00 00e0 user assigned interrupt 8 0x00 0100 user assigned interrupt 9 0x00 0120 user assigned interrupt 10 0x00 0140 user assigned interrupt 11 0x00 0160 user assigned interrupt 12 0x00 0180 user assigned interrupt 13 0x00 01a0 user assigned interrupt 14 0x00 01c0 user assigned interrupt? lowest priority 15 0x00 01e0 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 9 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 priority level of 11 are aliased to the lowest priority bit position (15) in these registers and share vector address 0x00 01e0. interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. interrupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the emulation, power-down, and reset interrupts are nonmaskable with the imask register, but software can use the dis int instruction to mask the power-down interrupt. the interrupt control (icntl) register controls interrupt nesting and enables or disables interrupts globally. the gen- eral-purpose programmable flag (pfx) pins can be configured as outputs, can implement software interrupts, and (as inputs) can implement hardware interrupts. pro- grammable flag pin interrupts can be configured for level-sensitive, single edge-sensitive, or dual edge- sensitive operation. the irptl register is used to force and clear interrupts. on-chip stacks preserve the processor status and are auto- matically maintained during interrupt handling. to support interrupt, loop, and subroutine nesting, the pc stack is 33 levels deep, the loop stack is eight levels deep, and the status stack is 16 levels deep. to prevent stack overflow, the pc stack can generate a stack-level interrupt if the pc stack falls below three locations full or rises above 28 locations full. the following instructions globally enable or disable interrupt servicing, regardless of the state of imask. ena int; dis int; at reset, interrupt servicing is disabled. for quick servicing of interrupts, a secondary set of dag and computational registers exist. switching between the primary and secondary registers lets programs quickly service interrupts, while preserving the dsp?s state. dma controller the adsp-2195 has a dma controller that supports automated data transfers with minimal overhead for the dsp core. cycle stealing dma transfers can occur between the adsp-2195?s internal memory and any of its dma-capable peripherals. additionally, dma transfers can be accomplished between any of the dma-capable peripherals and external devices connected to the external memory interface. dma-capable peripherals include the host port, sports, spi ports, and uart. each individual dma-capable peripheral has a dedicated dma channel. to describe each dma sequence, the dma controller uses a table 2. peripheral interrupts and priority at reset interrupt id reset priority slave dma/host port interface 0 0 sport0 receive 1 1 sport0 transmit 2 2 sport1 receive 3 3 sport1 transmit 4 4 sport2 receive/spi0 5 5 sport2 transmit/spi1 6 6 uart receive 7 7 uart transmit 8 8 timer a 9 9 timer b 10 10 timer c 11 11 programmable flag 0 (any pfx) 12 11 programmable flag 1 (any pfx) 13 11 memory dma port 14 11 table 3. interrupt control (icntl) register bits bit description 0?3 reserved 4 interrupt nesting enable 5 global interrupt enable 6 reserved 7 mac-biased rounding enable 8?9 reserved 10 pc stack interrupt enable 11 loop stack interrupt enable 12?15 reserved for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 10 rev. pra set of parameters?called a dma descriptor. when succes- sive dma sequences are needed, these dma descriptors can be linked or chained together, so the completion of one dma sequence auto-initiates and starts the next sequence. dma sequences do not contend for bus access with the dsp core, instead dmas ?steal? cycles to access memory. all dma transfers use the dma bus shown in the func- tional block diagram on page 1 . because all of the peripherals use the same bus, arbitration for dma bus access is needed. the arbitration for dma bus access appears in table 4 . host port the adsp-2195?s host port functions as a slave on the external bus of an external host. the host port interface lets a host read from or write to the dsp?s memory space, boot space, or internal i/o space. examples of hosts include external microcontrollers, microprocessors, or asics. the host port is a multiplexed address and data bus that provides both an 8-bit and a 16-bit data path and operates using an asynchronous transmission protocol. through this port, an off-chip host can directly access the dsp?s entire memory space map, boot memory space, and internal i/o space. to access the dsp?s internal memory space, a host steals one cycle per access from the dsp. a host access to the dsp?s external memory uses the external port interface and does not stall (or steal cycles from) the dsp?s core. because a host can access internal i/o memory space, a host can control any of the dsp?s i/o mapped peripherals. the host port is most efficient when using the dsp as a slave and uses dma to automate the incrementing of addresses for these accesses. in this case, an address does not have to be transferred from the host for every data transfer. host port acknowledge (hack) modes the host port supports a number of modes (or protocols) for generating a hack output for the host. the host selects ack or ready modes using the hack_p and hack pins. the host port also supports two modes for address control: address latch enable (ale) and address cycle control (acc) modes. the dsp auto-detects ale versus acc mode from the hale and hwr inputs. the host port hack signal polarity is selected (only at reset) as active high or active low, depending on the value driven on the hack_p pin.the hack polarity is stored into the host port configuration register as a read only bit. the dsp uses hack to indicate to the host when to complete an access. for a read transaction, a host can proceed and complete an access when valid data is present in the read buffer and the host port is not busy doing a write. for a write transactions, a host can complete an access when the write buffer is not full and the host port is not busy doing a write. two mode bits in the host port configuration register hpcr [7:6] define the functionality of the hack line. hpcr6 is initialized at reset based on the values driven on hack and hack_p pins (shown in table 5 ); hpcr7 is always cleared (0) at reset. hpcr [7:6] can be modified after reset by a write access to the host port configuration register. table 4. i/o bus arbitration priority dma bus master arbitration priority sport0 receive dma 0?highest sport1 receive dma 1 sport2 receive dma 2 sport0 transmit dma 3 sport1 transmit dma 4 sport2 transmit dma 5 spi0 receive/transmit dma 6 spi1 receive/transmit dma 7 uart receive dma 8 uart transmit dma 9 host port dma 10 memory dma 11?lowest table 5. host port acknowledge mode selection values driven at reset hpcr [7:6] initial values acknowledge mode hack_p hack bit 7 bit 6 0 0 0 1 ready mode 0 1 00ack mode 1 0 00ack mode 1 1 0 1 ready mode this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 11 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 the functional modes selected by hpcr [7:6] are as follows (assuming active high signal): ack mode ?acknowledge is active on strobes; hack goes high from the leading edge of the strobe to indicate when the access can complete. after the host samples the hack active, it can complete the access by removing the strobe.the host port then removes the hack. ready mode ?r e a d y a c t i v e o n s t r o b e s , g o e s l o w t o i n s e r t wait state during the access.if the host port can not complete the access, it de-asserts the hack/ready line. in this case, the host has to extend the access by keeping the strobe asserted. when the host samples the hack asserted, it can then proceed and complete the access by de-asserting the strobe. while in address cycle control (acc) mode and the ack or ready acknowledge modes, the hack is returned active for any address cycle. host port chip selects there are two chip-select signals associated with the host port: hcms and hcioms . the host chip memory select (hcms ) lets the host select the dsp and directly access the dsp?s internal/external memory space or boot memory space. the host chip i/o memory select (hcioms ) lets the host select the dsp and directly access the dsp?s internal i/o memory space. before starting a direct access, the host configures host port interface registers, specifying the width of external data bus (8- or 16-bit) and the target address page (in the ijpg register). the dsp generates the needed memory select signals during the access, based on the target address. the host port interface combines the data from one, two, or three consecutive host accesses (up to one 24-bit value) into a single dma bus access to prefetch host direct reads or to post direct writes. during assembly of larger words, the host port interface asserts ack for each byte access that does not start a read or complete a write. otherwise, the host port interface asserts ack when it has completed the memory access successfully. dsp serial ports (sports) the adsp-2195 incorporates three complete synchronous serial ports (sport0, sport1, and sport2) for serial and multiprocessor communications. the sports support the following features: bidirectional operation?each sport has independent transmit and receive pins. buffered (8-deep) transmit and receive ports?each port has a data register for transferring data words to and from other dsp components and shift registers for shifting data in and out of the data registers. clocking?each transmit and receive port can either use an external serial clock ( 75 mhz) or generate its own, in frequencies ranging from 1144 hz to 75 mhz. word length?each sport supports serial data words from 3 to 16 bits in length transferred in big endian (msb) or little endian (lsb) format. framing?each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. companding in hardware?each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. dma operations with single-cycle overhead?each sport can automatically receive and transmit multiple buffers of memory data, one data word each dsp cycle. either the dsp?s core or a host processor can link or chain sequences of dma transfers between a sport and memory. the chained dma can be dynamically allocated and updated through the dma descriptors (dma transfer parameters) that set up the chain. interrupts?each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through dma. multichannel capability?each sport supports the h.100 standard. serial peripheral interface (spi) ports the dsp has two spi-compatible ports that enable the dsp to communicate with multiple spi-compatible devices. these ports are multiplexed with sport2, so either sport2 or the spi ports are active, depending on the state of the opmode pin during hardware reset. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosix, and master input-slave output, misox) and a clock pin (serial clock, sckx). two spi chip select input pins (spissx ) let other spi devices select the dsp, and fourteen spi chip select output pins (spixsel7?1) let the dsp select other spi devices. the spi select pins are reconfigured programmable flag pins. using these pins, the spi ports provide a full duplex, synchronous serial interface, which supports both master and slave modes and multimaster environments. each spi port?s baud rate and clock phase/polarities are programmable (see figure 4 ), and each has an integrated dma controller, configurable to support both transmit and receive data streams. the spi?s dma controller can only service unidirectional accesses at any given time. figure 4. spi clock rate calculation spi clock rate hclk 2 spibaud -------------------------------------- = for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 12 rev. pra during transfers, the spi ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. the serial clock line synchronizes the shifting and sampling of data on the two serial data lines. in master mode, the dsp?s core performs the following sequence to set up and initiate spi transfers: 1. enables and configures the spi port?s operation (data size, and transfer format). 2. selects the target spi slave with an spixsely output pin (reconfigured programmable flag pin). 3. defines one or more dma descriptors in page 0 of i/o memory space (optional in dma mode only). 4. enables the spi dma engine and specifies transfer direction (optional in dma mode only). 5. in non-dma mode only, reads or writes the spi port receive or transmit data buffer. the sckx line generates the programmed clock pulses for simultaneously shifting data out on mosix and shifting data in on misox. in dma mode only, transfers continue until the spi dma word count transitions from 1 to 0. in slave mode, the dsp?s core performs the following sequence to set up the spi port to receive data from a master transmitter: 1. enables and configures the spi slave port to match the operation parameters set up on the master (data size and transfer format) spi transmitter. 2. defines and generates a receive dma descriptor in page 0 of memory space to interrupt at the end of the data transfer (optional in dma mode only). 3. enables the spi dma engine for a receive access (optional in dma mode only). 4. starts receiving the data on the appropriate spi sckx edges after receiving an spi chip select on an spissx input pin (reconfigured programmable flag pin) from a master in dma mode only, reception continues until the spi dma word count transitions from 1 to 0. the dsp?s core could continue, by queuing up the next dma descriptor. a slave mode transmit operation is similar, except the dsp?s core specifies the data buffer in memory space from which to transmit data, generates and relinquishes control of the transmit dma descriptor, and begins filling the spi port?s data buffer. if the spi controller isn?t ready on time to transmit, it can transmit a ?zero? word. uart port the uart port provides a simplified uart interface to another peripheral or host. it performs full duplex, asyn- chronous transfers of serial data. options for the uart include support for 5?8 data bits; 1 or 2 stop bits; and none, even, or odd parity. the uart port supports two modes of operation: pio (programmed i/o) the dsp?s core sends or receives data by writing or reading i/o-mapped uatx or uarx registers, respec- tively. the data is double-buffered on both transmit and receive. dma (direct memory access) the dma controller transfers both transmit and receive data. this reduces the number and frequency of inter- rupts required to transfer data to and from memory. the uart has two dedicated dma channels. these dma channels have lower priority than most dma channels because of their relatively low service rates. the uart?s baud rate (see figure 5 ), serial data format, error code generation and status, and interrupts are programmable: supported bit rates range from 95 bits to 6.25m bits per second (100 mhz peripheral clock). supported data formats are 7- or 12-bit frames. transmit and receive status can be configured to generate maskable interrupts to the dsp?s core. the timers can be used to provide a hardware-assisted autobaud detection mechanism for the uart interface. programmable flag (pfx) pins the adsp-2195 has 16 bidirectional, general-purpose i/o, programmable flag (pf15?0) pins. the pf7?0 pins are dedicated to general-purpose i/o. the pf15?8 pins serve either as general-purpose i/o pins (if the dsp is connected to an 8-bit external data bus) or serve as data15?8 lines (if the dsp is connected to a 16-bit external data bus). the programmable flag pins have special functions for clock multiplier selection and for spi port operation. for more information, see serial peripheral interface (spi) ports on figure 5. uart clock rate calculation 1 1 where d = 1 to 65536 uart clock rate hclk 16 d ------------------ = this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 13 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 page 11 and clock signals on page 14 . ten mem- ory-mapped registers control operation of the programmable flag pins: flag direction register specifies the direction of each individual pfx pin as input or output. flag control and status registers specify the value to drive on each individual pfx output pin. as input, software can predicate instruction execution on the value of individual pfx input pins captured in this register. one register sets bits, and one register clears bits. flag interrupt mask registers enable and disable each individual pfx pin to function as an interrupt to the dsp?s core. one register sets bits to enable interrupt function, and one register clears bits to disable interrupt function. input pfx pins function as hardware interrupts, and output pfx pins function as software interrupts?latching in the imask and irptl registers. flag interrupt polarity register specifies the polarity (active high or low) for interrupt sensitivity on each individual pfx pin. flag sensitivity registers specify whether individual pfx pins are level- or edge-sensitive and specify?if edge-sensitive?whether just the rising edge or both the rising and falling edges of the signal are significant. one register selects the type of sensitivity, and one register selects which edges are signif- icant for edge-sensitivity. low power operation the adsp-2195 has four low-power options that signifi- cantly reduce the power dissipation when the device operates under standby conditions. to enter any of these modes, the dsp executes an idle instruction. the adsp-2195 uses configuration of the pdwn, stopck, and stopall bits in the pllctl register to select between the low-power modes as the dsp executes the idle. depending on the mode, an idle shuts off clocks to different parts of the dsp in the different modes. the low power modes are: idle power-down core power-down core/peripherals power-down all idle mode when the adsp-2195 is in idle mode, the dsp core stops executing instructions, retains the contents of the instruc- tion pipeline, and waits for an interrupt. the core clock and peripheral clock continue running. to enter idle mode, the dsp can execute the idle instruc- tion anywhere in code. to exit idle mode, the dsp responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the idle. power-down core mode when the adsp-2195 is in power-down core mode, the dsp core clock is off, but the dsp retains the contents of the pipeline and keeps the pll running. the peripheral bus keeps running, letting the peripherals receive data. to enter power-down core mode, the dsp executes an idle instruction after performing the following tasks: enter a power-down interrupt service routine check for pending interrupts and i/o service routines clear (= 0) the pdwn bit in the pllctl register clear (= 0) the stopall bit in the pllctl register set (= 1) the stopck bit in the pllctl register to exit power-down core mode, the dsp responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the idle. power-down core/peripherals mode when the adsp-2195 is in power-down core/peripherals mode, the dsp core clock and peripheral bus clock are off, but the dsp keeps the pll running. the dsp does not retain the contents of the instruction pipeline.the periph- eral bus is stopped, so the peripherals cannot receive data. to enter power-down core/peripherals mode, the dsp executes an idle instruction after performing the following tasks: enter a power-down interrupt service routine check for pending interrupts and i/o service routines clear (= 0) the pdwn bit in the pllctl register set (= 1) the stopall bit in the pllctl register to exit power-down core/peripherals mode, the dsp responds to an interrupt and (after five to six cycles of latency) resumes executing instructions with the instruction after the idle. power-down all mode when the adsp-2195 is in power-down all mode, the dsp core clock, the peripheral clock, and the pll are all stopped. the dsp does not retain the contents of the instruction pipeline. the peripheral bus is stopped, so the peripherals cannot receive data. to enter power-down all mode, the dsp executes an idle instruction after performing the following tasks: enter a power-down interrupt service routine check for pending interrupts and i/o service routines set (= 1) the pdwn bit in the pllctl register for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 14 rev. pra to exit power-down core/peripherals mode, the dsp responds to an interrupt and (after 500 cycles to re-stab ilize the pll) resumes executing instructions with the instruc- tion after the idle. clock signals the adsp-2195 can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscil- lator. if a crystal oscillator is used, the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 6 . capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. a parallel-resonant, funda- mental frequency, microprocessor-grade crystal should be used for this configuration. if a buffered, shaped clock is used, this external clock connects to the dsp?s clkin pin. clkin input cannot be halted, changed, or operated below the specified frequency during normal operation. this clock signal should be a ttl-compatible signal. when an external clock is used, the xtal input must be left unconnected. the dsp provides a user-programmable 1 to 32 multi- plication of the input clock, including some fractional values, to support 128 external to internal (dsp core) clock ratios. the msel6?0, bypass, and df pins decide the pll multiplication factor at reset. at runtime, the multipli- cation factor can be controlled in software. to support input clocks greater that 100 mhz, the pll uses an additional input: the divide frequency (df) pin. if the input clock is greater than 100 mhz, df must be high. if the input clock is less than 100 mhz, df must be low. the combination of pullup and pull-down resistors in figure 6 set up a core clock ratio of 6:1, which produces a 150 mhz core clock from the 25 mhz input. for other clock multiplier settings, see the adsp-219x/2191 dsp hardware reference . the peripheral clock is supplied to the clkout pin. all on-chip peripherals for the adsp-2195 operate at the rate set by the peripheral clock. the peripheral clock is either equal to the core clock rate or one-half the dsp core clock rate. this selection is controlled by the iosel bit in the pllctl register. the maximum core clock is 160 mhz, and the maximum peripheral clock is 100 mhz?the combination of the input clock and core/peripheral clock ratios may not exceed these limits. reset the reset signal initiates a master reset of the adsp-2195. the reset signal must be asserted during the power-up sequence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock to stabilize. if reset is activated any time after power up, the clock does not continue to run and requires stabilization time when recovering from reset. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 100 s ensures that the pll has locked, but does not include the crystal oscillator start-up time. during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulsewidth specification, t rsp . the reset input contains some hysteresis. if using an rc circuit to generate your reset signal, the circuit should use an external schmidt trigger. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and resets all registers to their default values (where applicable). when reset is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is per- formed. program control jumps to the location of the on-chip boot rom (0xff0000). power supplies the adsp-2195 has separate power supply connections for the internal (v ddint ) and external (v ddext ) power supplies. the internal supply must meet the 2.5 v requirement. the external supply must be connected to a 3.3 v supply. all external supply pins must be connected to the same supply. figure 6. external crystal connections & & ! ") ) ) ' ' ) 0 + ( ( % - - & . - 1 ) 0 & )' 0 &. this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 15 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 as indicated in table 6 , the opmode pin has a dual role, acting as a boot mode select during reset and determining sport or spi operation at runtime. if the opmode pin at reset is the opposite of what is needed in an application during runtime, the application needs to set the opmode bit appropriately during runtime prior to using the corre- sponding peripheral. booting modes the adsp-2195 has seven mechanisms (listed in table 6 ) for automatically loading internal program memory after reset. the opmode, bmode1, and bmode0 pins, sampled during hardware reset, and three bits in the reset configu- ration register implement these modes: execute from memory external 16 bits?the memory boot routine located in boot rom memory space executes a boot-stream-formatted program located at address 0x10000 of boot memory space, packing 16-bit external data into 24-bit internal data. the external port interface is configured for the default clock multiplier (128) and read waitstates (7). boot from eprom?the eprom boot routine located in boot rom memory space executes a boot-stream-for- matted program located at address 0x00000 of boot memory space, packing 8- or 16-bit external data into 24-bit internal data. the external port interface is con- figured for the default clock multiplier (32) and read waitstates (7). boot from host?the (8- or 16-bit) host downloads a boot-stream-formatted program to internal or external memory. the host?s boot routine is located in internal rom memory space and uses the top 16 locations of page 0 program memory and the top 272 locations of page 0 data memory. the internal boot rom sets semaphore a (an io register within the host port) and then polls until the semaphore is reset. once detected, the internal boot rom will remap the interrupt vector table to page 0 internal memory and jump to address 0x0000 internal. from the point of view of the host interface, an external host has full control of the dsp's memory map. the host has the freedom to directly write internal memory, external memory, and internal i/o memory space. the dsp core execution is held off until the host clears the semaphore register. this strategy allows the maximum flexibility for the host to boot in the program and data code, by leaving it up to the programmer. execute from memory external 8 bits (no boot)? execution starts from page 1 of external memory space, packing either 8- or 16-bit external data into 24-bit internal data. the external port interface is configured for the default clock multiplier (128) and read waitstates (7). boot from uart?the host downloads boot-stream-formatted program using an autobaud handshake sequence. the host agent selects a baud rate within the uart?s clocking capabilities. after a hardware reset, the dsp?s uart transmits 0xff values (eight bits data, one start bit, one stop bit, no parity bit) until detecting the start of the first memory block. the uart boot routine is located in internal rom memory space and uses the top 16 locations of page 0 program memory and the top 272 locations of page 0 data memory. boot from spi, up to 4k bits?the spi0 port uses the spi0sel1 (reconfigured pf2) output pin to select a single serial eprom device, submits a read command at address 0x00, and begins clocking consecutive data into internal or external memory. use only spi-compatible eproms of 4k bit (12-bit address range). the spi0 boot routine located in internal rom memory space executes a boot-stream-formatted program, using the top 16 locations of page 0 program memory and the top 272 locations of page 0 data memory. the spi boot configu- ration is spibaud0=60 (decimal), cpha=1, cpol=1, 8-bit data, and msb first. boot from spi, from >4k bits to 512k bits?the spi0 port uses the spi0sel1 (re-configured pf2) output pin to select a single serial eprom device, submits a read command at address 0x00, and begins clocking consecu- tive data into internal or external memory. use only spi-compatible eproms of 4k bit (16-bit address range). the spi0 boot routine located in internal rom memory space executes a boot-stream-formatted program, using the top 16 locations of page 0 program memory and the top 272 locations of page 0 data memory. table 6. select boot mode (opmode, bmode1, and bmode0) opmode bmode1 bmode0 function 0 0 0 execute from external memory 16 bits (no boot) 001boot from eprom 010boot from host 0 1 1 reserved 1 0 0 execute from external memory 8 bits (no boot) 101boot from uart 1 1 0 boot from spi, up to 4k bits 1 1 1 boot from spi, >4k bits up to 512k bits for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 16 rev. pra bus request and bus grant the adsp-2195 can relinquish control of the data and address buses to an external device. when the external device requires access to the bus, it asserts the bus request (br ) signal. the (br ) signal is arbitrated with core and peripheral requests. external bus requests have the lowest priority. if no other internal request is pending, the external bus request will be granted. due to synchronizer and arbi- tration delays, bus grants will be provided with a minimum of three peripheral clock delays. the adsp-2195 will respond to the bus grant by: three-stating the data and address buses and the ms3?0 , bms , ioms , rd , and wr output drivers. asserting the bus grant (bg ) signal. the adsp-2195 will halt program execution if the bus is granted to an external device and an instruction fetch or data read/write request is made to external general-purpose or peripheral memory spaces. if an instruction requires two external memory read accesses, the bus will not be granted between the two accesses. if an instruction requires an external memory read and an external memory write access, the bus may be granted between the two accesses. the external memory interface can be configured so that the core will have exclusive use of the interface. dma and bus requests will be granted. when the external device releases br , the dsp releases bg and continues program execution from the point at which it stopped. the bus request feature operates at all times, even while the dsp is booting and reset is active. the adsp-2195 asserts the bgh pin when it is ready to start another external port access, but is held off because the bus was previously granted. this mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems. instruction set description the adsp-2195 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. the assembly language, which takes full advantage of the processor?s unique architecture, offers the following benefits: adsp-219x assembly language syntax is a superset of and source-code-compatible (except for two data registers and dag base address registers) with adsp-218x family syntax. it may be necessary to restructure adsp-218x programs to accommodate the adsp-2195?s unified memory space and to conform to its interrupt vector map. the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. every instruction, but two, assembles into a single, 24-bit word that can execute in a single instruction cycle. the exceptions are two dual word instructions. one writes 16- or 24-bit immediate data to memory, and the other is an absolute jump/call with the 24-bit address specified in the instruction. multifunction instructions allow parallel execution of an arithmetic, mac, or shift instruction with up to two fetches or one write to processor memory space during a single instruction cycle. program flow instructions support a wider variety of con- ditional and unconditional jumps/calls and a larger set of conditions on which to base execution of conditional instructions. development tools the adsp-2195 is supported with a complete set of software and hardware development tools, including analog devices? emulators and visualdsp++? development envi- ronment. the same emulator hardware that supports other adsp-219x dsps, also fully emulates the adsp-2195. the visualdsp++ project management environment lets programmers develop and debug an application. this envi- ronment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simula- tor, a c/c++ compiler, and a c/c++ run-time library that includes dsp and mathematical functions. two key points for these tools are: compiled adsp-219x c/c++ code efficiency?the compiler has been developed for efficient translation of c/c++ code to adsp-219x assembly. the dsp has architectural features that improve the efficiency of compiled c/c++ code. adsp-218x family code compatibility?the assembler has legacy features to ease the conversion of existing adsp-218x applications to the adsp-219x. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: view mixed c/c++ and assembly code (interleaved source and object information) insert break points set conditional breakpoints on registers, memory, and stacks trace instruction execution perform linear or statistical profiling of program execution fill, dump, and graphically plot the contents of memory source level debugging create custom debugger windows the visualdsp++ ide lets programmers define and manage dsp software development. its dialog boxes and property pages let programmers configure and manage all this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 17 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 of the adsp-219x development tools, including the syntax highlighting in the visualdsp++ editor. this capability permits: control how the development tools process inputs and generate outputs. maintain a one-to-one correspondence with the tool?s command line switches. analog devices? dsp emulators use the ieee 1149.1 jtag test access port of the adsp-2195 processor to monitor and control the target board processor during emulation. the emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. nonintrusive in-circuit emulation is assured by the use of the processor?s jtag interface?the emulator does not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the adsp-219x processor family. hardware tools include adsp-219x pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the white mountain dsp (product line of analog devices, inc.) family of emulators are tools that every dsp developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halted to send data and commands, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the target?s design must include the interface between an analog devices? jtag dsp and the emulation header on a custom dsp target board. target board header the emulator interface to an analog devices? jtag dsp is a 14-pin header, as shown in figure 7 . the customer must supply this header on the target board in order to commu- nicate with the emulator. the interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1" spacing, with a minimum post length of 0.235". pin 3 is the key position used to prevent the pod from being inserted backwards. this pin must be clipped on the target board. also, the clearance (length, width, and height) around the header must be considered. leave a clearance of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector. as can be seen in figure 7 , there are two sets of signals on the header. there are the standard jtag signals tms, tck, tdi, tdo, trst , and emu used for emulation purposes (via an emulator). there are also secondary jtag signals btms, btck, btdi, and btrst that are option- ally used for board-level (boundary scan) testing. when the emulator is not connected to this header, place jumpers across btms, btck, btrst , and btdi as shown in figure 8 . this holds the jtag signals in the correct state to allow the dsp to run free. remove all the jumpers when connecting the emulator to the jtag header. figure 7. jtag target board connector for jtag equipped analog devices dsp (jumpers in place) figure 8. jtag target board connector with no local boundary scan (% "' " + ) & & & (% "' " + ) & & & for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 18 rev. pra jtag emulator pod connector figure 9 details the dimensions of the jtag pod connector at the 14-pin target end. figure 10 displays the keep-out area for a target board header. the keep-out area allows the pod connector to properly seat onto the target board header. this board area should contain no components (chips, resistors, capacitors, etc.). the dimensions are referenced to the center of the 0.25" square post pin. design-for-emulation circuit information for details on target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website (www.ana- log.com)?use site search on ?ee-68?. this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a general overview of the adsp-2195 architecture and functionality. for detailed information on the adsp-219x family core architecture and instruction set, refer to the adsp-219x/2191 dsp hardware reference . pin descriptions adsp-2195 pin definitions are listed in table 7 . all adsp-2195 inputs are asynchronous and can be asserted asynchronously to clkin (or to tck for trst ). unused inputs should be tied or pulled to v ddext or gnd, except for addr21?0, data15?0, pf7-0, and inputs that have internal pull-up or pull-down resistors (trst , bmode0, bmode1, opmode, bypass, tck, tms, tdi, and reset )?these pins can be left floating. these pins have a logic-level hold circuit that prevents input from floating internally. the following symbols appear in the type column of table 7 : g = ground, i = input, o = output, p = power supply, and t = three-state. figure 9. jtag pod connector dimensions figure 10. jtag pod connector keep-out area '. 2 '.2 '. 2 '.'2 '.)2 table 7. pin descriptions pin type function a21?0 o/t external port address bus d7?0 i/o/t external port data bus, least significant 8 bits d15 /pf15 /spi1sel7 i/o/t i/o i data 15 (if 16-bit external bus)/programmable flags 15 (if 8-bit external bus)/spi1 slave select output 7 (if 8-bit external bus, when spi1 enabled) d14 /pf14 /spi0sel7 i/o/t i/o i data 14 (if 16-bit external bus)/programmable flags 14 (if 8-bit external bus)/spi0 slave select output 7 (if 8-bit external bus, when spi0 enabled) d13 /pf12 /spi1sel6 i/o/t i/o i data 13 (if 16-bit external bus)/programmable flags 13 (if 8-bit external bus)/spi1 slave select output 6 (if 8-bit external bus, when spi1 enabled) d12 /pf12 /spi0sel6 i/o/t i/o i data 12 (if 16-bit external bus)/programmable flags 12 (if 8-bit external bus)/spi0 slave select output 6 (if 8-bit external bus, when spi0 enabled) this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 19 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 d11 /pf11 /spi1sel5 i/o/t i/o i data 11 (if 16-bit external bus)/programmable flags 11 (if 8-bit external bus)/spi1 slave select output 5 (if 8-bit external bus, when spi1 enabled) d10 /pf10 /spi0sel5 i/o/t i/o i data 10 (if 16-bit external bus)/programmable flags 10 (if 8-bit external bus)/spi0 slave select output 5 (if 8-bit external bus, when spi0 enabled) d9 /pf9 /spi1sel4 i/o/t i/o i data 9 (if 16-bit external bus)/programmable flags 9 (if 8-bit external bus)/spi1 slave select output 4 (if 8-bit external bus, when spi1 enabled) d8 /pf8 /spi0sel4 i/o/t i/o i data 8 (if 16-bit external bus)/programmable flags 8 (if 8-bit external bus)/spi0 slave select output 4 (if 8-bit external bus, when spi0 enabled) pf7 /spi1sel3 /df i/o/t i i programmable flags 7/spi1 slave select output 3 (when spi0 enabled)/divisor frequency (divisor select for pll input during boot) pf6 /spi0sel3 /msel6 i/o/t i i programmable flags 6/spi0 slave select output 3 (when spi0 enabled)/multiplier select 6 (during boot) pf5 /spi1sel2 /msel5 i/o/t i i programmable flags 5/spi1 slave select output 2 (when spi0 enabled)/multiplier select 5 (during boot) pf4 /spi0sel2 /msel4 i/o/t i i programmable flags 4/spi0 slave select output 2 (when spi0 enabled)/multiplier select 4 (during boot) pf3 /spi1sel1 /msel3 i/o/t i i programmable flags 3/spi1 slave select output 1 (when spi0 enabled)/multiplier select 3 (during boot) pf2 /spi0sel1 /msel2 i/o/t i i programmable flags 2/spi0 slave select output 1 (when spi0 enabled)/multiplier select 2 (during boot) pf1 /spiss1 /msel1 i/o/t i i programmable flags 1/spi1 slave select input (when spi1 enabled)/multiplier select 1 (during boot) pf0 /spiss0 /msel0 i/o/t i i programmable flags 0/spi0 slave select input (when spi0 enabled)/multiplier select 0 (during boot) rd o/t external port read strobe wr o/t external port write strobe ack i external port access ready acknowledge bms o/t external port boot space select ioms o/t external port io space select table 7. pin descriptions (continued) pin type function for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 20 rev. pra ms3?0 o/t external port memory space selects br iexternal port bus request bg oexternal port bus grant bgh oexternal port bus grant hang had15?0 i/o/t host port multiplexed address and data bus ha16 i host port msb of address bus hack_p i host port ack polarity hrd ihost port read strobe hwr ihost port write strobe hack o host port access ready acknowledge hale i host port address latch strobe or address cycle control hcms i host port internal memory?internal i/o memory?boot memory select hcioms i host port internal i/o memory select clkin i clock input/oscillator input xtal o oscillator output bmode1?0 i boot mode 1?0. the bmode1 and bmode0 pins have 85 k ? internal pull-up resistors. opmode i operating mode. the opmode pin has a 85 k ? internal pull-up resistor. clkout o clock output bypass i phase-lock-loop (pll) bypass mode. the bypass pin has a 85 k ? internal pull-up resistor. rclk1?0 i/o/t sport1?0 receive clock rclk2/sck1 i/o/t sport2 receive clock/spi1 serial clock rfs1?0 i/o/t sport1?0 receive frame sync rfs2/mosi1 i/o/t sport2 receive frame sync/spi1 master-output, slave-input data tclk1?0 i/o/t sport1?0 transmit clock tclk2/sck0 i/o/t sport2 transmit clock/spi0 serial clock tfs1?0 i/o/t sport1?0 transmit frame sync tfs2/mosi0 i/o/t sport2 transmit frame sync/spi0 master-output, slave-input data dr1?0 i/t sport1?0 serial data receive dr2/miso1 i/o/t sport2 serial data receive/spi1 master-input, slave-output data dt1?0 o/t sport1?0 serial data transmit table 7. pin descriptions (continued) pin type function this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 21 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 dt2/miso0 i/o/t sport2 serial data transmit/spi0 master-input, slave-output data tmr2?0 i/o/t timer output or capture rxd i uart serial receive data txd o uart serial transmit data reset i processor reset. resets the adsp-2195 to a known state and begins execution at the program memory location specified by the hardware reset vector address. the reset input must be asserted (low) at power-up. the reset pin has a 85 k ? internal pull-up resistor. tck i test clock (jtag). provides a clock for jtag boundary scan. the tck pin has a 85 k ? internal pull-up resistor. tms i test mode select (jtag). used to control the test state machine. the tms pin has a 85 k ? internal pull-up resistor. tdi i test data input (jtag). provides serial data for the boundary scan logic. the tdi pin has a 85 k ? internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan path. trst i test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-2195. the trst pin has a 65 k ? internal pull-down resistor. emu o emulation status (jtag). must be connected to the adsp-2195 emulator target board connector only. v ddint p core power supply. nominally 2.5 v dc and supplies the dsp?s core processor. (four pins). v ddext p i/o power supply; nominally 3.3 v dc. (nine pins). gnd g power supply return. (twelve pins). nc do not connect. reserved pins that must be left open and unconnected. table 7. pin descriptions (continued) pin type function for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 22 rev. pra specifications recommended operating conditions parameter description 1 1 specifications subject to change without notice. min max unit v ddint internal (core) supply voltage 2.37 2.63 v v ddext external (i/o) supply voltage tbd 3.6 v v ih1 high level input voltage 2 , @ v ddint = max 2 applies to input and bidirectional pins: data15?0, had15?0, ha16, hale, hack, hack_p, bypass, hrd , hwr , ack, pf7?0, hcms , hcioms , br , tfs0, tfs1, tfs2/mosi0, rfs0, rfs1, rfs2/mosi1, opmode, bmode1?0, tms, tdi, tck, dt2/miso0, dr0, dr1, dr2/miso1, tclk0, tclk1, tclk2/sck0, rclk0, rclk1, rclk2/sck1. 2.0 v ddext v v ih2 high level input voltage 3 , @ v ddint = max 3 applies to input pins: clkin, reset , trst . 2.2 v ddext v v il low level input voltage 2 , @ v ddint = min ?0.3 0.6 v t amb ambient operating temperature 0 70 oc electrical characteristics parameter 1 description test conditions min typical max unit v oh high level output voltage 2 @ v ddext = min, i oh = ?0.5 ma 2.4 v v ol low level output voltage 2 @ v ddext = min, i ol = 2.0 ma 0.4 v i ih high level input current 3, 4 @ v ddext = max, v in = v dd max tbd a i il low level input current 2 @ v ddext = max, v in = 0 v tbd a i inp high level input current 5 @ v ddext = max, v in = v dd max tbd a i ilp low level input current 3 @ v ddext = max, v in = 0 v tbd a i ozh three-state leakage current 6 @ v ddext = max, v in = v dd max 10 a i ozl three-state leakage current 5 @ v ddext = max, v in = 0 v 10 a i dd-idle1 supply current (core) idle1 pll enabled, cclk = 160 mhz 7 ma this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 23 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 i dd-idle2 supply current (core) idle2 pll enabled, hclk = 80 mhz, cclk disabled 7 1ma i dd-typical supply current (core) typical hclk = 80 mhz, cclk = 160 mhz 7,8 184 ma i dd-peak supply current (core) peak hclk = 80 mhz, cclk = 160 mhz 7,8 215 ma i dd-peripheral1 supply current (peripheral) pll enabled, core, hclk, clkin disabled 7 5ma i dd-peripheral2 supply current (peripheral) hclk = 80 mhz 7 60 ma i dd-powerdown supply current pll, core, hclk, clkin disabled 7 100 a c in input capacitance 9, 10 f in = 1 mhz, t case = 25c, v in = 2.5 v tbd pf 1 specifications subject to change without notice. 2 applies to output and bidirectional pins: data15?0, addr21?0, had15?0, ms3?0 , ioms , rd , wr , clkout, hack, pf7?0, tmr2?0, bgh , bg , dt0, dt1, dt2/miso0, tclk0, tclk1, tclk2/sck0, rclk0, rclk1, rclk2/sck1, tfs0, tfs1, tfs2/mosi0, rfs0, rfs1, rfs2/mosi1, bms , tdo, txd, emu . 3 applies to input pins: ack, br , hcms , hcioms , opmode, bmode1?0, ha16, hale, hrd , hwr , clkin, reset , tck, tdi, tms, trst , dr0, dr1, bypass, rxd. 4 applies to input pins with internal pull-ups: bmode0, bmode1, opmode, bypass, tck, tms, tdi, reset . 5 applies to input pin with internal pull-down: trst 6 applies to three-statable pins: data15?0, addr21?0, ms3?0 , rd , wr , pf7?0, bms , ioms , tfsx, rfsx, tdo, emu . 7 test conditions: @ v ddint = 2.5v, t amb = 25oc 8 refer to table 23 on page 52 for definitions of operation types. 9 applies to all signal pins. 10 guaranteed, but not tested. electrical characteristics (continued) parameter 1 description test conditions min typical max unit for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 24 rev. pra absolute maximum ratings esd sensitivity timing specifications this section contains timing information for the dsp?s external signals. v ddint internal (core) supply voltage 1,2 .......?0.3 to 3.0 v 1 specifications subject to change without notice. 2 stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v ddext external (i/o) supply voltage ............?0.3 to 4.6 v v il ?v ih input voltage ......................?0.5 to v ddext +0.5 v v ol ?v oh output voltage swing ........?0.5 to v ddext +0.5 v c l load capacitance............................................ 200 pf t cclk core clock period........................................ 6.25 ns f cclk core clock frequency.............................. 160 mhz t hclk peripheral clock period................................... 10 ns f hclk peripheral clock frequency...................... 100 mhz t store storage temperature range .............. ?65 to 150oc t lead lead temperature (5 seconds)...................... 185oc caution: esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-2195 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid perfor- mance degradation or loss of functionality. this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 25 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 clock in and clock out cycle timing table 8 and figure 11 describe clock and reset operations. per v ddint internal (core) supply voltage, ?0.3 to 3.0 v on page 24 , combinations of clkin and clock multipliers must not select core/peripheral clocks in excess of 160/100 mhz. table 8. clock in and clock out cycle timing parameter description min max unit switching characteristic t ckod clkout delay from clkin 0 5.8 ns t cko clkout period 1 1 figure 11 shows a 2 ratio between clkout = 2 clkin (or t hclk = 2 t cclk ), but the ratio has many programmable options. for more information see the system design chapter of the adsp-219x/2191 dsp hardware reference . 10 ns timing requirements t ck clkin period 2,3 2 in clock multiplier mode and msel6?0 set for 1:1 (or clkin=cclk), t ck =t cclk . 3 in bypass mode, t ck =t cclk . 6.25 200 ns t ckl clkin low pulse 2.2 ns t ckh clkin high pulse 2.2 ns t wrst reset asserted pulsewidth low 200t clkout ns t msls mselx/bypass stable before reset asserted setup 160 s t mslh mselx/bypass stable after reset de-asserted hold 1000 ns figure 11. clock in and clock out cycle timing 3 & & *' & 3 % 3 & 3 & 3 & 3 3 & 3 3 3 for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 26 rev. pra programmable flags cycle timing table 9 and figure 12 describe programmable flag operations. table 9. programmable flags cycle timing parameter description min max unit switching characteristic t dfo flag output delay with respect to hclk 3 ns t hfo flag output hold after hclk high tbd tbd ns timing requirement t hfi flag input hold is asynchronous 3 ns figure 12. programmable flags cycle timing fla g in put 3 & 3 3 3 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 27 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 timer pwm_out cycle timing table 10 and figure 13 describe timer expired operations. the input signal is asynchronous in ?width capture mode? and has an absolute maximum input frequency of 50 mhz. table 10. timer pwm_out cycle timing parameter description min max unit switching characteristic t hto timer pulsewidth output 1 1 the minimum time for t hto is one cycle, and the maximum time for t hto equals (2 32 ?1) cycles. 6.25 (2 32 ?1) cycles ns figure 13. timer pwm_out cycle timing & %, 3 for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 28 rev. pra external port write cycle timing table 11 and figure 14 describe external port write operations. the external port lets systems extend read/write accesses in three ways: waitstates, ack input, and combined waitstates and ack. to add waits with ack, the dsp must see ack low at the rising edge of emi clock. ack low causes the dsp to wait, and the dsp requires two emi clock cycles after ack goes high to finish the access. for more information, see the external port chapter in the adsp-219x/2191 dsp hardware reference table 11. external port write cycle timing parameter description 1, 2, 3 1 t hclk is the peripheral clock period. 2 these are preliminary timing parameters that are based on worst-case operating conditions. 3 the pad loads for these timing parameters are 20 pf. min max unit switching characteristics t cwa emi 4 clock low to wr asserted delay 4 emi clock is the external port clock that is generated from the emi clock ratio. this signal is not available on an external pi n, but (roughly) corresponds to hclk (at similar clock ratios). 2.8 ns t csws chip select asserted to wr de-asserted delay 4.3 6.5 ns t aws address valid to wr setup and delay 4.9 7.0 ns t aks ack asserted to emi clock high delay 6.0 ns t wscs wr de-asserted to chip select de-asserted 4.8 7.0 ns t wsa wr de-asserted to address invalid 4.5 6.6 ns t cwd emi clock low to wr de-asserted delay 2.5 2.7 ns t ww wr strobe pulsewidth t hclk ?0.5 ns t cda wr to data enable access delay 1.5 4.1 ns t cdd wr to data disable access delay 3.3 7.4 ns t dsw data valid to wr de-asserted setup t hclk ?1.4 t hclk +4.8 ns t dhw wr de-asserted to data invalid hold time; wt_hold=0 3.4 7.4 ns t dhw wr de-asserted to data invalid hold time; wt_hold=1 t hclk +3.4 t hclk +7.4 ns timing requirement t akw ack strobe pulsewidth 10.0 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 29 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 14. external port write cycle timing )* ' 3 % 3 % 3 % 3 %% 3 &% 3 % 3 % 3 & % * ' *' & 3 % 3 % 3 % 3 3 & for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 30 rev. pra external port read cycle timing table 12 and figure 15 describe external port read operations. for additional information on the ack signal, see the discussion on on page 28 . table 12. external port read cycle timing parameter description 1, 2, 3 1 t hclk is the peripheral clock period. 2 these are preliminary timing parameters that are based on worst-case operating conditions. 3 the pad loads for these timing parameters are 20 pf. min max unit switching characteristics t cra emi 4 clock low to rd asserted delay 4 emi clock is the external port clock that is generated from the emi clock ratio. this signal is not available on an external pi n, but (roughly) corresponds to hclk (at similar clock ratios). 2.8 ns t csrs chip select asserted to rd asserted delay 4.3 6.5 ns t ars address valid to rd setup and delay 4.9 7.0 ns t aks ack asserted to emi clock high delay 6.0 ns t crd emi clock low to rd de-asserted delay 2.5 2.7 ns t rscs rd de-asserted to chip select de-asserted setup 4.8 7.0 ns t rw rd strobe pulsewidth t hclk ?0.5 ns t rsa rd de-asserted to address invalid setup 4.5 6.6 ns timing requirements t akw ack strobe pulsewidth 10.0 ns t cda rd to data enable access delay 0.0 ns t rda rd asserted to data access setup t hclk ?5.5 ns t ada address valid to data access setup t hclk ?0.2 ns t sda chip select asserted to data access setup t hclk ?0.6 ns t sd data valid to rd de-asserted setup 1.8 ns t hrd rd de-asserted to data invalid hold 0.0 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 31 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 15. external port read cycle timing )*' 3 3 3 3 % 3 &% 3 3 3 3 3 3 & *' * ' & 3 3 3 3 & for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 32 rev. pra external port bus request and grant cycle timing table 13 and figure 16 describe external port bus request and bus grant operations. table 13. external port bus request and grant cycle timing parameter description 1, 2, 3 1 t hclk is the peripheral clock period. 2 these are preliminary timing parameters that are based on worst-case operating conditions. 3 the pad loads for these timing parameters are 20 pf. min max unit switching characteristics t sd clkout high to xms , address, and rd /wr disable 4.3 ns t se clkout low to xms , address, and rd /wr enable 4.0 ns t dbg clkout high to bg asserted setup 2.2 ns t ebg clkout high to bg de-asserted hold time 2.2 ns t dbh clkout high to bgh asserted setup 2.4 ns t ebh clkout high to bgh de-asserted hold time 2.4 ns timing requirements t bs br asserted to clkout high setup 4.6 ns t bh clkout high to br de-asserted hold time 0.0 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 33 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 16. external port bus request and grant cycle timing 3 *' *' & 3 3 3 3 3 3 3 3 3 3 3 % for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 34 rev. pra host port ale mode write cycle timing table 14 and figure 17 describe host port write operations in address latch enable (ale) mode. for more information on ack, ready, ale, and acc mode selection, see the host port modes description on page 10 . table 14. host port ale mode write cycle timing parameter description min max unit switching characteristics t whks hwr asserted to hack asserted (setup, ack mode) 0.6 0.6+t nh 1 1 t nh are peripheral bus latencies (n t hclk ); these are internal dsp latencies related to the number of peripherals attempting to access dsp memory at the same time. ns t whkh hwr de-asserted to hack de-asserted (hold, ack mode) 2ns t whs hwr asserted to hack asserted (setup, ready mode) 0.6 ns t whh hwr asserted to hack de-asserted (hold, ready mode) 2+t nh 1 ns timing requirements t csal hcms or hcioms asserted to hale asserted 0ns t alpw hale asserted pulsewidth 4 ns t alcsw hale de-asserted to hcms or hcioms de-asserted 1 ns t wcsw hwr de-asserted to hcms or hcioms de-asserted 1 ns t alw hale de-asserted to hwr asserted 1 ns t wcs hwr de-asserted (after last byte) to hcms or hcioms de-asserted (ready for next write) 1ns t hkwd hack asserted to hwr de-asserted (hold, ack mode) 1.5 ns t aals address valid to hale de-asserted (setup) 4 ns t alah hale de-asserted to address invalid (hold) 1.5 ns t dws data valid to hwr de-asserted (setup) 4 ns t wdh hwr de-asserted to data invalid (hold) 1 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 35 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 17. host port ale mode write cycle timing 3 ( ( ( ( ! % % )* ' 3 % 3 3 % 3 3 % & 3 % % & & 3 % & & & & 3 % 3 % 3 % 3 &% 3 % % 3 % 3 % for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 36 rev. pra host port acc mode write cycle timing table 15 and figure 18 describe host port write operations in address cycle control (acc) mode. for more information on ack, ready, ale, and acc mode selection, see the host port modes description on page 10 . table 15. host port acc mode write cycle timing parameter description min max unit switching characteristics t whks hwr asserted to hack asserted (setup, ack mode) 0.6 0.6+t nh 1 1 t nh are peripheral bus latencies (n t hclk ); these are internal dsp latencies related to the number of peripherals attempting to access dsp memory at the same time. ns t whkh hwr de-asserted to hack de-asserted (hold, ack mode) 2ns t whs hwr asserted to hack asserted (setup, ready mode) 0.6 ns t whh hwr asserted to hack de-asserted (hold, ready mode) 2+t nh 1 ns timing requirements t wal hwr asserted to hale de-asserted (delay) 1.5 ns t csal hcms or hcioms asserted to hale asserted (delay) 0ns t alcs hale de-asserted to optional hcms or hcioms de-asserted 1ns t wcsw hwr de-asserted to hcms or hcioms de-asserted 1 ns t alw hale asserted to hwr asserted 0.5 ns t csw hcms or hcioms asserted to hwr asserted 12ns t wcs hwr de-asserted (after last byte) to hcms or hcioms de-asserted (ready for next write) 1ns t alew hale de-asserted to hwr asserted 1 ns t hkwd hack asserted to hwr de-asserted (hold, ack mode) 1.5 ns t adw address valid to hwr asserted (setup) 4 ns t wad hwr de-asserted to address invalid (hold) 1 ns t dws data valid to hwr de-asserted (setup) 4 ns t wdh hwr de-asserted to data invalid (hold) 1 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 37 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 18. host port acc mode write cycle timing & 3 % )*' 3 % ( ( ( ( ! % % 3 % 3 % 3 % & 3 % & 3 3 % % 3 % & & 3 &% & & 3 % 3 3 % 3 % 3 % % 3 % 3 % for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 38 rev. pra host port ale mode read cycle timing table 16 and figure 19 describe host port read operations in address latch enable (ale) mode. for more information on ack, ready, ale, and acc mode selection, see the host port modes description on page 10 . table 16. host port ale mode read cycle timing parameter description min max unit switching characteristics t rhks hrd asserted to hack asserted (setup, ack mode) 22+t nh 1 1 t nh are peripheral bus latencies (n t hclk ); these are internal dsp latencies related to the number of peripherals attempting to access dsp memory at the same time. ns t rhkh hrd de-asserted to hack de-asserted (hold, ack mode) 2ns t rhs hrd asserted to hack asserted (setup, ready mode) 2ns t rhh hrd asserted to hack de-asserted (hold, ready mode) 2+t nh 1 ns timing requirements t csal hcms or hcioms asserted to hale asserted (delay) 0ns t alcs hale de-asserted to optional hcms or hcioms de-asserted 1ns t rcsw hrd de-asserted to hcms or hcioms de-asserted 1 ns t alr hale de-asserted to hrd asserted 1 ns t rcs hrd de-asserted (after last byte) to hcms or hcioms de-asserted (ready for next read) 1ns t alpw hale asserted pulsewidth 4 ns t hkrd hack asserted to hrd de-asserted (hold, ack mode) 1.5 ns t aals address valid to hale de-asserted (setup) 4 ns t alah hale de-asserted to address invalid (hold) 1 ns t rdh hrd de-asserted to data invalid (hold) 1 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 39 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 19. host port ale mode read cycle timing )* ' 3 ( ( ( ( ! % % 3 3 3 3 & & 3 & & & 3 % 3 3 & 3 3 % & & 3 3 3 & for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 40 rev. pra host port acc mode read cycle timing table 17 and figure 20 describe host port read operations in address cycle control (acc) mode. for more information on ack, ready, ale, and acc mode selection, see the host port modes description on page 10 . table 17. host port acc mode read cycle timing parameter description min max unit switching characteristics t rhks hrd asserted to hack asserted (setup, ack mode) 11+t nh 1 1 t nh are peripheral bus latencies (n t hclk ); these are internal dsp latencies related to the number of peripherals attempting to access dsp memory at the same time. ns t rhkh hrd de-asserted to hack de-asserted (hold, ack mode) 2ns t rhs hrd asserted to hack asserted (setup, ready mode) 1ns t rhh hrd asserted to hack de-asserted (hold, ready mode) 2+t nh 1 ns timing requirements t csal hcms or hcioms asserted to hale asserted (delay) 0ns t alcs hale de-asserted to optional hcms or hcioms de-asserted 1ns t rcsw hrd de-asserted to hcms or hcioms de-asserted 1 ns t alw hale asserted to hwr asserted 0.5 ns t aler hale de-asserted to hwr asserted 1 ns t csr hcms or hcioms asserted to hrd asserted 12ns t rcs hrd de-asserted (after last byte) to hcms or hcioms de-asserted (ready for next read) 1ns t wal hwr de-asserted to hale de-asserted (delay) 1.5 ns t hkrd hack asserted to hrd de-asserted (hold, ack mode) 1.5 ns t adw address valid to hwr de-asserted (setup) 4 ns t wad hwr de-asserted to address invalid (hold) 1 ns t rdh hrd de-asserted to data invalid (hold) 1 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 41 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 20. host port acc mode read cycle timing 3 )* ' 3 % 3 % ( ( ( ( ! % % 3 & 3 & 3 3 & 3 % 3 % & & & 3 % 3 3 3 3 % & & & 3 3 for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 42 rev. pra serial port (sport) clocks and data timing table 18 and figure 21 describe sport transmit and receive operations. table 18. serial port (sport) clocks and data timing 1 1 to determine whether communication is possible between two devices at clock speed n, the following specifications must be confi rmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. parameter description min max unit switching characteristics t hofse rfs hold after rclk (internally generated rfs) 2 2 referenced to drive edge. 012.4ns t dfse rfs delay after rclk (internally generated rfs) 2 012.4ns t ddten transmit data delay after tclk 2 012.1ns t ddtte data disable from external tclk 2 012.0ns t ddtin data enable from internal tclk 2 06.8ns t ddtti data disable from internal tclk 2 06.3ns timing requirements t sclkiw tclk/rclk width 20 ns t sfsi tfs/rfs setup before tclk/rclk 3 3 referenced to sample edge. ?0.6 ns t hfsi tfs/rfs hold after tclk/rclk 3, 4 4 rfs hold after rclk when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tclk for late external tfs is 0 ns mini mum from drive edge. ?0.3 ns t sdri receive data setup before rclk 3 ?2.3 ns t hdri receive data hold after rclk 3 1.9 ns t sclkw tclk/rclk width 20 ns t sfse tfs/rfs setup before tclk/rclk 3 ?0.6 ns t hfse tfs/rfs hold after tclk/rclk 3, 4 ?0.6 ns t sdre receive data setup before rclk 3 ?2.2 ns t hdre receive data hold after rclk 3 1.8 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 43 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 21. serial port (sport) clocks and data 3 3 3 ( ( & 3 3 & & ! & ( 4 ! & 3 &% 3 3 3 3 1 & ! & ( . & ( 4 & 3 &% 3 3 3 3 3 & 3 3 ( ( for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 44 rev. pra serial port (sport) frame synch timing table 19 and figure 22 describe sport frame synch operations. to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) r/tclk width. table 19. serial port (sport) frame synch timing parameter description min max unit switching characteristics t hofse rfs hold after rclk (internally generated rfs) 1 1 referenced to drive edge. 12.4 ns t hofsi tfs hold after tclk (internally generated tfs) 1 12.2 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 2 2 mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs . 4.7 ns t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 3 4.7 ns t hdte transmit data hold after tclk (external clk) 1 12.4 ns t hdti transmit data hold after tclk (internal clk) 1 012.2ns t ddte transmit data delay after tclk (external clk) 1 012.2ns t ddti transmit data delay after tclk (internal clk) 1 011.1ns timing requirements t sfse tfs/rfs setup before tclk/rclk (external clk) 3 3 referenced to sample edge. ?0.6 tbd ns t sfsi tfs/rfs setup before tclk/rclk (internal clk) 3 ?0.6 tbd ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 45 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 22. serial port (sport) frame synch ( ( & 3 3 3 3 ! ! ( % 5 - 5 ' ( ( & 3 3 3 3 3 3 3 3 for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 46 rev. pra serial peripheral interface (spi) port?master timing table 20 and figure 23 describe spi port master operations. table 20. serial peripheral interface (spi) port?master timing parameter description min max unit switching characteristics t sdscim spixsel low to first sclk edge (x=0 or 1) 2t hclk ns t spichm serial clock high period 2t hclk ns t spiclm serial clock low period 2t hclk ns t spiclk serial clock period 4t hclk ns t hdsm last sclk edge to spixsel high (x=0 or 1) 2t hclk ns t spitdm sequential transfer delay 2t hclk ns t ddspid sclk edge to data out valid (data out delay) 0 6 ns t hdspid sclk edge to data out invalid (data out hold) 0 5 ns timing requirements t sspid data input valid to sclk edge (data input setup) 1.6 ns t hspid sclk sampling edge to data input invalid 1.6 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 47 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 23. serial peripheral interface (spi) port?master 3 3 3 3 3 # # 5 ' 67 & 5 ' & 5 3 3 3 3 & 3 3 3 3 ( ( 3 3 3 5 5' ( 3 3 ( for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 48 rev. pra serial peripheral interface (spi) port?slave timing table 21 and figure 24 describe spi port slave operations. table 21. serial peripheral interface (spi) port?slave timing parameter description min max unit switching characteristics t dsoe spiss assertion to data out active 06ns t dsdhi spiss deassertion to data high impedance 06ns t ddspid sclk edge to data out valid (data out delay) 0 5 ns t hdspid sclk edge to data out invalid (data out hold) 0 5 ns timing requirements t spichs serial clock high period 2t hclk ns t spicls serial clock low period 2t hclk ns t spiclk serial clock period 4t hclk ns t hds last spiclk edge to spiss not asserted 2t hclk ns t spitds sequential transfer delay 2t hclk ns t sdsci spiss assertion to first spiclk edge 2t hclk ns t sspid data input valid to sclk edge (data input setup) 1.6 ns t hspid sclk sampling edge to data input invalid 1.6 ns this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 49 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 figure 24. serial peripheral interface (spi) port?slave 3 3 3 ( 3 3 3 3 3 & 5 ' & 5 3 3 3 3 3 & 3 3 3 3 3 ( ( 3 3 3 ( 5 5' 3 for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 50 rev. pra universal asynchronous receiver-transmitter (uart) port?receive and transmit timing figure 25 describes uart port receive and transmit oper- ations. the maximum baud rate is hclk/16. as shown in figure 25 there is some latency between the generation internal uart interrupts and the external data operations. these latencies are negligible at the data transmission rates for the uart. figure 25. uart port?receive and transmit timing ! )* ( ( 8 & & ! )* * 8 % ( % this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 51 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 jtag test and emulation port timing table 22 and figure 26 describe jtag port operations. table 22. jtag port timing parameter description min max unit switching characteristics t dtdo tdo delay from tck low 4 ns t dsys system outputs delay after tck low 1 05ns timing parameters t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck low 2 4ns t hsys system inputs hold after tck low 2 5ns t trstw trst pulsewidth 3 4ns 1 system outputs = data15?0, addr21?0, ms3?0 , rd , wr , ack, clkout, bg , pf7?0, timexp, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, bms . 2 system inputs = data15?0, addr21?0, rd , wr , ack, br , bg , pf7?0, dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, clkin, reset . 3 50 mhz max. figure 26. jtag port timing & 3 & 3 3 3 3 3 3 for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 52 rev. pra output drive currents figure 27 shows typical i-v characteristics for the output drivers of the adsp-2195. the curves represent the current drive capability of the output drivers as a function of output voltage. power dissipation total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execution sequence and the data operands involved. using the current current-versus-operation infor- mation in table 23 , designers can estimate the adsp-2195?s internal power supply (v ddint ) input current for a specific application, according to the formula in figure 28 . the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: the number of output pins that switch during each cycle (o) the maximum frequency at which they can switch (f) their load capacitance (c) their voltage swing (v dd ) and is calculated by the formula in figure 29 . figure 27. adsp-2195 typical drive currents ( ! ( * ( *' ' .) '.) .) .' .) .' ( ! * 9 *'' *' * ' * ' *' ' ' ' ' ' '' ' table 23. adsp-2195 operation types versus input current activity i dd (ma) 1 cclk = 80 mhz i dd (ma) 1 cclk = 160 mhz core peripheral core peripheral power down 2 0000 idle 1 3 0305 idle 2 4 030060 ty p i c a l 5 95 30 184 60 peak 6 112 30 215 60 1 test conditions: v dd = 2.50 v; hclk (peripheral clock) frequency = cclk/2 (core clock/2) frequency; t amb = 25 oc. 2 pll, core, peripheral clocks, and clkin are disabled. 3 pll is enabled and core and peripheral clocks are disabled. 4 core clk is disabled and peripheral clock is enabled. this is a power- down interrupt mode. the timer can be used to generate a n interrupt to enable the core clock. 5 all instructions execute from internal memory. 100% of the instructions are mac with dual operand addressing, with changing dat a fetched using a linear address sequence, and 50% of the instructions move data from pm to a data register. 6 all instructions execute from internal memory. 50% of the instructions are repeat macs with dual operand addressing, with chang ing data fetched using a linear address sequence. figure 28. i ddint calculation i ddint %typical i dd-typical () = %idle i dd-idle () %powerdown i dd-pwrdwn () ++ this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 53 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 the load capacitance should include the processor?s package capacitance (c in ). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. for example, estimate p ext with the following assumptions: a system with one bank of external data memory?asyn- chronous ram (16-bit) one 64k 16 ram chip is used with a load of 10 pf maximum peripheral speed hclk = 100 mhz external data memory writes occur every other cycle, a rate of 1/(4t hclk ), with 50% of the pins switching the bus cycle time is 100 mhz (t hclk = 10 nsec) figure 29. p ext calculation p ext oc v dd 2 f = this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 54 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 the p ext equation is calculated for each class of pins that can drive as shown in table 24 . a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipa- tion with the formula in figure 30 . where: p ext is from table 24 p int is i ddint 2.5v, using the calculation i ddint listed in power dissipation on page 52 note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. test conditions the dsp is tested for output enable, disable, and hold time. output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the equation in figure 31 . the output disable time t dis is the difference between t measured and t decay as shown in figure 32 . the time t measured is the interval from when the reference signal switches to when the output voltage decays ?v from the measured output high or output low voltage. the t decay is calculated with test loads c l and i l , and with ?v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 32 ). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. table 24. p ext calculation pin type # of pins % switching c f v dd 2 = p ext address 15 50 tbd pf 25.0 mhz 10.9 v = tbd w msx 10 tbdpf 25.0 mhz 10.9 v = tbd w wr 1? tbdpf 25 mhz 10.9 v = tbd w data 16 50 tbd pf 25.0 mhz 10.9 v = tbd w clkout 1 ? tbd pf 100 mhz 10.9 v = tbd w p ext =tbd w figure 30. p total (typical) calculation figure 31. decay time calculation p total p = ext p int + t decay c l v ? i l --------------- = figure 32. output enable/disable 3 ( ( * ( ( : ( 3 ( ( .'( .'( . ( ! .)( ( 3 3 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 55 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given in figure 31 . choose ?v to be the difference between the adsp-2195?s output voltage and the input threshold for the device requiring the hold time. a typical ?v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 37 ). the delay and hold specifications given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figure 35 and figure 36 show how output rise time varies with capaci- tance. these figures also show graphically how output delays and holds vary with load capacitance. (note that this graph or derating does not apply to output disable delays; see output disable time on page 54 .) the graphs in these figures may not be linear outside the ranges shown. environmental conditions the thermal characteristics in which the dsp is operating influence performance. thermal characteristics the adsp-2195 comes in a 144-lead lqfp or 144-lead ball grid array (mini-bga) package. the adsp-2195 is specified for an ambient tem- perature (t amb ) as calculated using the formula in figure 38 . to ensure that the t amb data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. a heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. where: t amb = ambient tempera- ture (measured near top surface of package) pd = power dissipation in w (this value depends upon the specific applica- tion; a method for calculating pd is shown under power dissipation). ca = value from table 25 . jb = tbdc/w there are some important things to note about these t amb calculations and the values in table 25 : this represents thermal resistance at total power of tbd w. for the lqfp package: jc = 0.96c/w for the mini-bga package: jc = 8.4c/w figure 33. equivalent device loading for ac measurements (includes all fixtures) :.)( )'; figure 34. voltage reference levels for ac measurements (except output enable/disable) .)( .)( figure 35. typical output rise time (10%?90%, v ddext =max) vs. load capacitance *; .' .' ' ' '' ' ' ' ' '' ' ' ' ' .' .' .' .' '.' .' * <= '.) ( * . ( - '>*"'> for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 56 rev. pra figure 36. typical output rise time (10%-90%, v ddext =min) vs. load capacitance figure 37. typical output delay or hold vs. load capacitance (at max case temperature) figure 38. t case calculation table 25. ca va lu e s 1 airflow (linear ft./min.) 0 100 200 400 600 airflow (meters/second) 00.5123 lqfp: ca (c/w) 44.3 41.4 38.5 35.3 32.1 mini-bga: ca (c/w) 26 24 22 20.9 19.8 .) ' .' .) .' .) .' '.) *; ' '' ' ' ' ' '' ' ' ' ' * <= '. * .- '>*"'> *; ) * ) '' )' +) '' ) )' +) * <= t amb t case = pd ca ? for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 57 rev. pra 1 these are preliminary estimates. for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 58 rev. pra adsp-2195 144-lead lqfp pinout table 26 lists the lqfp pinout by signal name. table 26. 144-lead lqfp pins (alphabetically by signal) signal pin # a0 84 a1 85 a2 86 a3 87 a4 88 a5 89 a6 91 a7 92 a8 93 a9 95 a10 96 a11 97 a12 98 a13 99 a14 101 a15 102 a16 103 a17 104 a18 106 a19 107 a20 108 a21 109 ack 120 bg 111 bgh 110 bmode0 70 bmode1 71 bms 113 br 112 bypass 72 clkout 130 d0 123 d1 124 d2 125 d3 126 d4 128 d5 135 d6 136 d7 137 d8 138 d9 139 d10 140 d11 141 d12 142 d13 144 d14 1 d15 2 dr0 60 dr1 67 dr2 49 dt0 56 dt1 64 dt2 46 emu 81 hack 26 hack_p 24 table 26. 144-lead lqfp pins (alphabetically by signal) (continued) signal pin # had0 3 had1 4 had2 6 had3 7 had4 8 had5 9 had6 10 had7 11 had8 12 had9 14 had10 15 had11 17 had12 18 had13 20 had14 21 had15 22 ha16 23 hale 30 hcms 27 hcioms 28 hrd 31 hwr 32 ioms 114 ms0 115 ms1 116 ms2 117 ms3 119 opmode 83 clkin 132 xtal 133 table 26. 144-lead lqfp pins (alphabetically by signal) (continued) signal pin # pf0 34 pf1 35 pf2 36 pf3 37 pf4 38 pf5 39 pf6 41 pf7 42 rclk0 61 rclk1 68 rclk2 50 reset 73 rfs0 62 rfs1 69 rfs2 51 rd 122 rxd 52 tck 78 tclk0 57 tclk1 65 tclk2 47 tdi 75 tdo 74 tfs0 59 tfs1 66 tfs2 48 tmr0 43 tmr1 44 tmr2 45 tms 76 table 26. 144-lead lqfp pins (alphabetically by signal) (continued) signal pin # for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 59 rev. pra table 27 lists the lqfp pinout by pin number. trst 79 txd 53 v ddext 13 v ddext 25 v ddext 40 v ddext 63 v ddext 90 v ddext 100 v ddext 118 v ddext 131 v ddext 143 v ddint 19 v ddint 58 v ddint 82 v ddint 127 gnd 5 gnd 16 gnd 29 gnd 33 gnd 54 gnd 55 gnd 77 gnd 80 gnd 94 gnd 105 gnd 129 gnd 134 wr 121 table 26. 144-lead lqfp pins (alphabetically by signal) (continued) signal pin # table 27. 144-lead lqfp pins (numerically by pin number signal pin # d14 1 d15 2 had0 3 had1 4 gnd 5 had2 6 had3 7 had4 8 had5 9 had6 10 had7 11 had8 12 v ddext 13 had9 14 had10 15 gnd 16 had11 17 had12 18 v ddint 19 had13 20 had14 21 had15 22 ha16 23 hack_p 24 v ddext 25 hack 26 hcms 27 hcioms 28 gnd 29 hale 30 hrd 31 hwr 32 gnd 33 pf0 34 pf1 35 pf2 36 pf3 37 pf4 38 pf5 39 v ddext 40 pf6 41 pf7 42 tmr0 43 tmr1 44 tmr2 45 dt2 46 tclk2 47 tfs2 48 dr2 49 rclk2 50 rfs2 51 rxd 52 txd 53 gnd 54 gnd 55 dt0 56 tclk0 57 v ddint 58 table 27. 144-lead lqfp pins (numerically by pin number (continued) signal pin # tfs0 59 dr0 60 rclk0 61 rfs0 62 v ddext 63 dt1 64 tclk1 65 tfs1 66 dr1 67 rclk1 68 rfs1 69 bmode0 70 bmode1 71 bypass 72 reset 73 tdo 74 tdi 75 tms 76 gnd 77 tck 78 trst 79 gnd 80 emu 81 v ddint 82 opmode 83 a0 84 a1 85 a2 86 a3 87 a4 88 table 27. 144-lead lqfp pins (numerically by pin number (continued) signal pin # for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 60 rev. pra a5 89 v ddext 90 a6 91 a7 92 a8 93 gnd 94 a9 95 a10 96 a11 97 a12 98 a13 99 v ddext 100 a14 101 a15 102 a16 103 a17 104 gnd 105 a18 106 a19 107 a20 108 a21 109 bgh 110 bg 111 br 112 bms 113 ioms 114 ms0 115 ms1 116 ms2 117 v ddext 118 table 27. 144-lead lqfp pins (numerically by pin number (continued) signal pin # this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 61 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 ms3 119 ack 120 wr 121 rd 122 d0 123 d1 124 d2 125 d3 126 v ddint 127 d4 128 gnd 129 clkout 130 v ddext 131 clkin 132 xtal 133 gnd 134 d5 135 d6 136 d7 137 d8 138 d9 139 d10 140 d11 141 d12 142 v ddext 143 d13 144 table 27. 144-lead lqfp pins (numerically by pin number (continued) signal pin # this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 62 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 adsp-2195 144-lead mini-bga pinout table 28 lists the mini-bga pinout by signal name. table 28. 144-lead mini-bga pins (alphabetically by signal) signal ball # a0 j11 a1 h9 a2 h10 a3 g12 a4 h11 a5 g10 a6 f12 a7 g11 a8 f10 a9 f11 a10 e12 a11 e11 a12 e10 a13 e9 a14 d11 a15 d10 a16 d12 a17 c11 a18 c12 a19 b12 a20 b11 a21 a11 ack a8 bg c10 bgh b10 bmode0 l10 bmode1 l9 bms a10 br b9 bypass m11 clkin a5 clkout c6 d0 d7 d1 a7 d2 c7 d3 a6 d4 b7 d5 a4 d6 c5 d7 b5 d8 d5 d9 a3 d10 c4 d11 b4 d12 c3 d13 a2 d14 b1 d15 b2 dr0 l7 dr1 k9 dr2 l5 tclk0 j6 dt1 l8 dt2 h4 emu j10 hack h3 hack_p g1 table 28. 144-lead mini-bga pins (alphabetically by signal) (continued) signal ball # this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 63 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 had0 c1 had1 b3 had2 c2 had3 d1 had4 d4 had5 d3 had6 d2 had7 e1 had8 e4 had9 e2 had10 f1 had11 e3 had12 f2 had14 f3 had15 g3 had13 g2 ha16 h2 hale j1 hcioms j3 hcms h1 hrd j2 hwr k2 ioms e8 ms0 d9 ms1 a9 ms2 c9 ms3 d8 opmode h12 pf0 k1 pf1 l1 table 28. 144-lead mini-bga pins (alphabetically by signal) (continued) signal ball # pf2 m2 pf3 l2 pf4 m3 pf5 l3 pf6 k3 pf7 m4 rclk0 k7 rclk1 j9 rclk2 j5 rd b8 reset l12 rfs0 k8 rfs1 m10 rfs2 m6 rxd k6 tck k11 dt0 h6 tclk1 m9 tclk2 k5 tdi k12 tdo l11 tfs0 m8 tfs1 j8 tfs2 m5 tmr0 k4 tmr1 l4 tmr2 j4 tms k10 trst j12 txd m7 table 28. 144-lead mini-bga pins (alphabetically by signal) (continued) signal ball # this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 64 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 table 29 lists the mini-bga pinout by ball number. v ddint d6 v ddint f4 v ddint g9 v ddint j7 v ddext e5 v ddext e6 v ddext f5 v ddext f6 v ddext g7 v ddext g8 v ddext h7 v ddext h8 gnd a1 gnd a12 gnd e7 gnd f7 gnd f8 gnd f9 gnd g4 gnd g5 gnd g6 gnd h5 gnd l6 gnd m1 gnd m12 wr c8 xtal b6 table 28. 144-lead mini-bga pins (alphabetically by signal) (continued) signal ball # table 29. 144-lead mini-bga pins (numerically by ball number) signal ball # gnd a1 d13 a2 d9 a3 d5 a4 clkin a5 d3 a6 d1 a7 ack a8 ms1 a9 bms a10 a21 a11 gnd a12 d14 b1 d15 b2 had1 b3 d11 b4 d7 b5 xtal b6 d4 b7 rd b8 br b9 bgh b10 a20 b11 a19 b12 had0 c1 had2 c2 d12 c3 d10 c4 d6 c5 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 65 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 clkout c6 d2 c7 wr c8 ms2 c9 bg c10 a17 c11 a18 c12 had3 d1 had6 d2 had5 d3 had4 d4 d8 d5 v ddint d6 d0 d7 ms3 d8 ms0 d9 a15 d10 a14 d11 a16 d12 had7 e1 had9 e2 had11 e3 had8 e4 v ddext e5 v ddext e6 gnd e7 ioms e8 a13 e9 a12 e10 a11 e11 table 29. 144-lead mini-bga pins (numerically by ball number) (continued) signal ball # a10 e12 had10 f1 had12 f2 had14 f3 v ddint f4 v ddext f5 v ddext f6 gnd f7 gnd f8 gnd f9 a8 f10 a9 f11 a6 f12 hack_p g1 had13 g2 had15 g3 gnd g4 gnd g5 gnd g6 v ddext g7 v ddext g8 v ddint g9 a5 g10 a7 g11 a3 g12 hcms h1 ha16 h2 hack h3 dt2 h4 gnd h5 table 29. 144-lead mini-bga pins (numerically by ball number) (continued) signal ball # this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 66 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 dt0 h6 v ddext h7 v ddext h8 a1 h9 a2 h10 a4 h11 opmode h12 hale j1 hrd j2 hcioms j3 tmr2 j4 rclk2 j5 tclk0 j6 v ddint j7 tfs1 j8 rclk1 j9 emu j10 a0 j11 trst j12 pf0 k1 hwr k2 pf6 k3 tmr0 k4 tclk2 k5 rxd k6 rclk0 k7 rfs0 k8 dr1 k9 tms k10 tck k11 table 29. 144-lead mini-bga pins (numerically by ball number) (continued) signal ball # tdi k12 pf1 l1 pf3 l2 pf5 l3 tmr1 l4 dr2 l5 gnd l6 dr0 l7 dt1 l8 bmode1 l9 bmode0 l10 tdo l11 reset l12 gnd m1 pf2 m2 pf4 m3 pf7 m4 tfs2 m5 rfs2 m6 txd m7 tfs0 m8 tclk1 m9 rfs1 m10 bypass m11 gnd m12 table 29. 144-lead mini-bga pins (numerically by ball number) (continued) signal ball # this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 67 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 outline dimensions . 144-lead metric thin plastic quad flatpack (lqfp) (st-144) 144-ball mini-bga (ca-144) . ' ! '.) '.') . ) . ' .) '.' ! '.+) '. ' '. ) + + + ' '" (% % '.'' $ .'' $ '.)' '.+ '. '.+ . % '.' - % . . 1 . . . .'' '.) '. '.) . % '.) - ( & . % '.' - ( . . 1 . . . . '.)) '.)' '. ) '.' ! .+' ! '.' .' $ & ' " + ) '.' '.'' $ "."' (% (% ! this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 68 rev. pra for current information contact analog devices at 800/262-5643 adsp-2195 september 2001 ordering guide part number 1, 2 1 st = plastic thin quad flatpack (lqfp). 2 ca = mini ball grid array ambient temperature range instruction rate on-chip sram operating voltage adsp-2195mkst-160x 0oc to 70oc 160 mhz 1.3m bit 2.5 int./3.3 ext. v adsp-2195mbst-140x -40oc to 85oc 140 mhz 1.3m bit 2.5 int./3.3 ext. v adsp-2195mkca-160x 0oc to 70oc 160 mhz 1.3m bit 2.5 int./3.3 ext. v ADSP-2195MBCA-140x -40oc to 85oc 140 mhz 1.3m bit 2.5 int./3.3 ext. v |
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